The present invention relates generally to semiconductor fabrication and more specifically to fabrication of 1T RAM structures.
Integration of memory in system-on-a-chips (SOC) is complicated due to the incompatibility of the memory process to the logic process. A 1T random access memory (RAM) structure was announced to alleviate the problem of process incompatibility. The 1T RAM structure consists of a metal-oxide semiconductor (MOS) transistor and a planar capacitor.
U.S. Pat. No. 5,510,284 to Yamauchi describes a process to form an asymmetric non-volatile memory.
U.S. Pat. No. 5,844,271 to Sethi et al. describes a gate with asymmetric source/drain regions.
U.S. Pat. No. 5,918,148 to Sato describes a 1T RAM process.
U.S. Pat. No. 6,316,320 to Nakahata et al. describes a 1T and one capacitor memory device.
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of integrating a 1T RAM in a CMOS process.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having a core area, a 1T RAM cell area and an I/O area is provided. A first poly gate is formed over the substrate within the core area with the first poly gate having exposed side walls. Respective pairs of capacitor plates and adjacent word lines are formed over the substrate within the 1T RAM cell area to form node junctions between the respective capacitor plates and adjacent word lines and a bit line contact junction between the word lines. The capacitor plates and the word lines each having exposed side walls. A second poly gate is formed over the substrate within the I/O area with the second poly gate having exposed side walls. First patterned masks are formed over the substrate to expose: the core area; the bit line contact junction; and portions of the node junctions adjacent the word lines. A first implantation is performed. A tilt implantation is performed. The first patterned masks are removed. Second patterned masks are formed over the substrate to expose: the I/O area and the 1T RAM cell area not within the bit line contact junction. A second implantation is performed. Sidewall spacers are formed so that the adjacent sidewall spacers between the respective pairs of capacitor plates and word lines being nearly merged. A third implantation is performed.